We propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnected by a\r\ngeneric three-stage three-sided rearrangeable polygonal switching network (PSN). The main component of this PSN consists of\r\na polygonal switch block interconnected by crossbars. In comparing our PSN with a three-stage three-sided clique-based (Xilinx\r\n4000-like FPGAs) (Palczewski; 1992) switching network of the same size and with the same number of switches, we find that the\r\nthree-stage three-sided clique-based switching network is not rearrangeable. Also, the effects of the rearrangeable structure and\r\nthe number of terminals on the network switch-efficiency are explored and a proper set of parameters is determined to minimize\r\nthe number of switches. Moreover, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch\r\nefficiency of PFPGA. Experiments on benchmark circuits show that switches and speed performance are significantly improved.\r\nBased on experiment results, we can determine the parameters of PFPGA for the VLSI implementation.
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